COMPUTERS · INSIDE THE TRANSISTOR

ACT 01 · CHIP — 19 billion switches

A phone chip from 2023, made on a “3 nm” process: about 104 square millimetres of silicon — smaller than a fingernail — carrying 19 billion transistors. Two performance CPU cores, four efficiency cores, a six-core GPU, a 16-core neural engine, caches, and the memory interfaces around the edge. Everything this phone computes is those transistors switching on and off. Pick an act, or drag the DIVE slider, and go down through six orders of magnitude to one of them.

  • FACT 19 billion transistors on 103.8 mm² — the A17 Pro, TSMC N3, 2023 [A17, TI].
  • COMPUTED That averages 183 million transistors per mm². Counting one a second would take 602 years.
  • ILLUSTRATION The block placement is drawn after published die-shot analyses, not copied from one.
sources
  • [A17] Apple, iPhone 15 Pro announcement, 12 Sep 2023 — A17 Pro: 3 nm, 19 billion transistors, 6-core CPU (2P+4E), 6-core GPU, 16-core Neural Engine.
  • [TI] TechInsights, Apple A17 Pro die analysis (2023) — 103.8 mm² die on TSMC N3; via Wikipedia, “Transistor count”.
  • [TC] Wikipedia, “Transistor count” — microprocessor table compiled from manufacturers' published figures (accessed Oct 2026).
  • [W3] Wikipedia, “3 nm process” — node name as marketing term; TSMC N3 45 nm CPP, N3E 48 nm CPP / 23 nm MMP; Intel 3 50 / 30 nm.
  • [IEDM22] TSMC, 3 nm CMOS FinFLEX platform, IEDM 2022 — N3 contacted gate pitch 45 nm; N3E minimum metal pitch 23 nm.
  • [IRDS] IEEE International Roadmap for Devices and Systems, More Moore, 2021/2022 — “3 nm” = 48 nm gate pitch, 24 nm metal pitch (G48M24); gate length near 16 nm.
  • [I22] C. Auth et al., “A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors”, VLSI 2012 — first FinFET in production; 90 nm gate pitch, 80 nm metal pitch.
  • [I14] S. Natarajan et al., Intel 14 nm, IEDM 2014 — 70 nm gate pitch, 52 nm metal pitch.
  • [I10] C. Auth et al., Intel 10 nm, IEDM 2017 — 54 nm gate pitch, 36 nm metal pitch.
  • [N7] TSMC N7 (S.-Y. Wu et al., IEDM 2016; WikiChip) — 57 nm gate pitch, 40 nm metal pitch.
  • [S3] Samsung Electronics, 30 Jun 2022 — start of 3 nm production with gate-all-around (MBCFET) transistors.
  • [HKMG] K. Mistry et al., “A 45nm logic technology with high-k + metal gate transistors”, IEDM 2007.
  • [Sze] S. M. Sze & K. K. Ng, Physics of Semiconductor Devices, 3rd ed. — subthreshold swing limit, Si properties, saturation velocity ~1×10⁷ cm/s.
  • [CODATA] NIST CODATA — lattice parameter of silicon a = 5.431 020 511 Å (22.5 °C).
  • [WR] N. Weste & D. Harris, CMOS VLSI Design, 4th ed. — the 6T SRAM cell, standard cells.
  • [BL] Nokia Bell Labs / IEEE Milestone “Invention of the First Transistor at Bell Telephone Laboratories, 1947”.
  • [Nobel] The Nobel Prize in Physics 1956 — Shockley, Bardeen and Brattain, “for their researches on semiconductors and their discovery of the transistor effect”.
  • [Moore] G. E. Moore, “Cramming more components onto integrated circuits”, Electronics 38(8), 1965; “Progress in digital integrated electronics”, IEDM 1975.
  • [Den] R. H. Dennard et al., “Design of ion-implanted MOSFET's with very small physical dimensions”, IEEE JSSC SC-9(5), 1974, 256–268.
  • [Clk] Intel and AMD launch specifications (ark.intel.com and press releases), 1971–2024; Intel's cancellation of the Tejas Pentium 4 successor for multicore, May 2004.

All geometry is modelled from published dimensions; no die photographs or third-party images are used. The chip's block placement is an illustration.

Next door: Inside the CPU — what billions of these switches add up to, one clock tick at a time.