building the bench…

MEMORY & STORAGE · ACT 01 — how far away is your data?

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A computer keeps the same kind of thing — a bit, a 0 or a 1 — in very different places, and the price of reaching each one differs by ten million times. The core's own L1 cache answers in about a nanosecond. Main memory takes about a hundred. An SSD, a hundred thousand. A spinning disk, ten million. Nanoseconds are too small to feel, so stretch them: if one nanosecond were one second, the L1 is a heartbeat, DRAM is a cup of coffee, the SSD is a day and a night, and the hard disk is a whole season. Pick a rung and fetch.

  • FACT Latencies are typical measured values for a 2020s desktop: L1 4–5 cycles, DRAM 70–100 ns, NVMe 4 KiB random read 50–150 µs, 7,200 rpm disk ~8 ms seek + 4.17 ms half-rotation. Your machine will differ.
  • ESTIMATE "If 1 ns were 1 s" multiplies every latency by a billion. It is exact arithmetic on rounded inputs.
  • MODEL The parts are drawn at their true sizes (DIMM 133 × 31 mm, M.2 SSD 80 × 22 mm, 3.5″ disk 147 × 102 mm); how they are laid out on the bench is illustrative.
sources
  • Dean J. "Numbers everyone should know", in Designs, Lessons and Advice from Building Large Distributed Systems (LADIS 2009) — the original latency ladder (L1 0.5 ns, DRAM 100 ns, disk seek 10 ms, CA↔Netherlands 150 ms).
  • Chips and Cheese, measured cache and memory latency of Zen 4, Golden Cove and Raptor Lake cores (2022–2024) — L1 4–5 cycles, L2 ~14–17, L3 ~40–70, DRAM ~70–100 ns.
  • Intel® 64 and IA-32 Architectures Optimization Reference Manual (2023) — Golden Cove 48 KiB L1D, 5-cycle load-to-use.
  • Yeap G et al. 5nm CMOS production technology platform. IEDM 2019 (0.021 µm² HD SRAM); Chang CH et al. IEDM 2022 (N3B 0.0199 µm²); TSMC N2 ISSCC/IEDM 2024 (~0.0175 µm²).
  • Holcomb DE, Burleson WP, Fu K. Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans Computers 2009;58(9):1198–1210.
  • JEDEC JESD79-4 DDR4 SDRAM (64 ms refresh window, tREFI 7.8 µs) and JESD79-5 DDR5 SDRAM (32 ms, tREFI 3.9 µs).
  • Liu J, Jaiyen B, Kim Y, Wilkerson C, Mutlu O. An experimental study of data retention behavior in modern DRAM devices. ISCA 2013 — retention spread and temperature dependence.
  • Hamamoto T, Sugiura S, Sawada S. On the retention time distribution of dynamic random access memory (DRAM). IEEE Trans Electron Devices 1998;45(6):1300–1309.
  • Halderman JA et al. Lest we remember: cold-boot attacks on encryption keys. USENIX Security 2008; Commun ACM 2009;52(5):91–98.
  • Micron Technology. 232-layer NAND: world's first six-plane TLC, 14.6 Gb/mm², two 116-layer decks (press materials, July 2022; IEEE Spectrum coverage).
  • SK hynix. Mass production of the world's first 321-high NAND begins (news release, 21 Nov 2024); Samsung 9th-gen V-NAND, 286 layers (2024).
  • JEDEC JESD218B Solid-State Drive (SSD) Requirements and Endurance Test Method — unpowered retention 1 year/30 °C (client), 3 months/40 °C (enterprise).
  • Compagnoni CM et al. Reviewing the evolution of the NAND flash technology. Proc IEEE 2017;105(9):1609–1633 — charge trap, MLC/TLC, cycling-induced threshold spread.
  • Seagate Exos X20 product manual (2021) — 7,200 rpm, 4.16 ms average latency; WD Ultrastar DC HC560 datasheet — ~7.7–8 ms average seek.
  • Juang JY, Bogy DB et al. thermal fly-height control sliders (CML Berkeley reports; UC San Diego dissertations) — head-disk spacing ~1–2 nm during read/write.
  • Weller D et al. A HAMR media technology roadmap to an areal density of 4 Tb/in². IEEE Trans Magn 2014;50(1) — PMR grain size ~8 nm, ~1 Tb/in².
  • Charap SH, Lu PL, He Y. Thermal stability of recorded information at high densities. IEEE Trans Magn 1997;33(1):978–983 — KᵤV/k_BT ≳ 60 for ten-year stability.
  • WonderNetwork global ping statistics, London ↔ New York (2024): ~70–75 ms; refractive index of silica fibre ≈ 1.47 (≈ 4.9 µs/km).

Every model on this page is built in code from published dimensions — no images or meshes are borrowed. Layouts of the boards and dies are illustrative; the sizes are real. Tags: FACT measured or specified · MODEL this page's own simplified simulation · ESTIMATE worked out from published figures · SPECULATION a roadmap, not a product.