THE PACKAGE

FACT is a published spec or standard. MODELLED is arithmetic on those specs — theoretical peaks and ideal timings; real programs land below them. DRAWN is a layout that shows the idea, not a die photo: the floorplan of SMs on the die, the inside of an SM, and which 12 SMs are off (it differs from chip to chip).

Live: act 06 is drawn by your own GPU through this page's WebGL, and its counts are read back from that frame. The teapot is the Utah teapot (Martin Newell, 1975), as built into three.js. Your GPU's name is read from the browser and never leaves the page.

The race compares an AMD Ryzen 9 7950X (16 cores, 2 × 256-bit FMA a core, ~5 GHz all-core, DDR5-5200 at 83.2 GB/s) with an H100 SXM5. The chain assumes a 3-cycle add on the CPU at 5.7 GHz and about 4 cycles on the GPU at 1.98 GHz — a model, not a benchmark.

• NVIDIA, H100 Tensor Core GPU Architecture whitepaper (2022)
• NVIDIA, H100 Tensor Core GPU datasheet
• NVIDIA Developer Blog, NVIDIA Hopper Architecture In-Depth (2022)
• NVIDIA, CUDA C++ Programming Guide — SIMT Architecture
• Lindholm et al., NVIDIA Tesla: A Unified Graphics and Computing Architecture, IEEE Micro 2008
• NVIDIA, PTX ISA — warp-level matrix multiply-accumulate (mma.m16n8k16)
• JEDEC JESD238, High Bandwidth Memory DRAM (HBM3)
• Khronos, WebGL 2.0 specification (OpenGL ES 3.0 pipeline)
• AMD, Ryzen 9 7950X specifications
• AMD, Software Optimization Guide for the AMD Zen 4 Microarchitecture (57647)
• Computer History Museum, the Utah teapot (Martin Newell, 1975)

Next: Inside the CPU — one core, one clock tick at a time. The LLM page — what all these matrix multiplies are for.